1. Field of the Invention
The present invention relates to a DRAM structure and fabrication method thereof, and especially relates to a DRAM structure with multiple memory cells sharing the same bit-line contact and fabrication method thereof.
2. Description of the Related Art
Recently, the capacitor has come to play a more and more important role in the design of semiconductor circuits, such as in DRAM, oscillators, time delay circuitry, ADC and DAC, etc.
The capacitor consists of two conducting plates (i.e. electrode plates) with an insulating material sandwiched between. The charging-storing capacity of the capacitor is determined by three physical characteristics: (1) the thickness of the insulating material; (2) the surface area of the electrode plate; and the (3) electrical or mechanic parameters of the insulating material and the plates.
In the case of DRAM, in order to fabricate a lot of memory cells in the same memory device, the base area of the memory cells must be small. At the same time, the electrode plates of the capacitors of the memory cells must have sufficient surface area to store enough charge.
Therefore, a three-dimensional stacked capacitor cell (STC) or trenched capacitor cell has been developed in a dense memory device. These capacitors form electrode plates of capacitors in the upper space of the storage devices in the silicon wafer or under the substrate. This kind of structure has the advantages of low soft error rate (SER) and capability of being attached with an insulating layer of high dielectric constant.
However, the size of the prior 3D capacitors is limited because of the difficulty in reducing the size of word-lines and bit-lines.
Referring to FIG. 1A, 1B and 1C FIG. 1A shows a layout of a DRAM array of the prior art, and FIG. 1B are a cross-sectional figure along line I--I in FIG. 1A. In a conventional DRAM array, an active region 50 is formed on a substrate 100, and is isolated by a field insulating layer 40. Word-lines WL1 and WL2, which serve as gates, cross over the active region 50. The parts of the active region 50 under the word-lines WL1 and WL2 serve as channel regions 11 and 12. The parts of the active region 50 outside the word-lines WL1 and WL2 serve as source regions S10 and S20. The part of the active region 50 between the word-lines WL1 and WL2 serves as a drain region D12. The bit-line BL is electrically connected to the drain region D12 through the contact BC.
The capacitors, such as stacked capacitors or french capacitors C10 and C20, are formed on the source regions. Other word-lines on the field insulating layer 40, such as word-lines WL3 and WL4, serve as gates of other memory cells.
In the conventional DRAM array, an active region 50 comprises two memory cells, with four word-lines WL1.about.WL4 passing through. One bit-line contact BC is only shared by two memory cells. Therefore, it is difficult to significantly reduce the size of device.